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preliminary 6021bs?atarm?07/04 features arm7tdmi ? arm ? thumb ? processor core ? high performance 32-bit risc ? high-density 16-bit instruction set (thumb) ? leader in mips/watt ? embedded ice (in circuit emulation) 16 kbytes internal sram fully programmable external bus interface (ebi) ? maximum external address space of 6 mbytes, up to four chip select lines 8-level priority, vectored interrupt controller ? three external interrupts including one fast interrupt line ten channel peripheral data controller (pdc) 57 programmable i/o lines four 16-bit general purpose timers (gpt) ? three configurable modes: counter, pwm, capture ? four external clock inputs, three multi-purpose i/o pins per timer four 16-bit simple timers (st) four channel 16-bit pulse width modulation (pwm) four can controllers 2.0a and 2.0b full can ? one with 32 buffers, three with 16 buffers two usarts ? support for j1587 and lin protocols one master/slave spi interface ? 8 to 16-bit programmable data length ? four external serial peripheral chip selects two 8-channel 10-bit analog to digital converters (adc) two 16-bit capture modules (capt) programmable watch timer (wt) programmable watchdog (wd) power management controller (pmc) ? 32 khz oscillator, main oscillator and pll ieee 1149.1 jtag boundary-scan on all digital pins fully static operation: 0 hz to 30 mhz at vddcore=3.3v, 85c 3.0v to 5.5v operating voltage range 3.0v to 3.6v core, memory and analog voltage range -40 to +85c operating temperature range available in a 176-lead lqfp package description the AT91SAM7A2 is based on the arm7tdmi embedded processor. this processor has a high-performance 32-bit risc architecture with a high-density 16-bit instruction set and very low power consumption. in addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. the AT91SAM7A2 has a direct connection to off-chip memory, including flash, through the fully programmable external bus interface. an 8-level priority vectored interrupt controller in conjunction with the peripheral data controller significantly improves the real time performance of the device. the device is manufactured using high-density cmos technology. by combining the arm7tdmi processor with an on-chip sram, and a wide range of peripheral functions, including usart, spi, can controllers, timer counter and ana- log-to-digital converters, on a monolithic chip, the AT91SAM7A2 is a powerful device that provides a flexible, cost-effective solution to many compute-intensive embedded control applications in the automotive and industrial world. at91 arm ? thumb ? - based microcontrollers AT91SAM7A2 summary
2 preliminary AT91SAM7A2 - summary 6021bs?atarm?07/04 block diagram figure 1. block diagram vrefp0 ana0in[7:0] vrefp1 ana1in[7:0] canrx0 cantx0 canrx1 cantx1 canrx2 cantx2 vddana vddio gnd nreset pwm0 add[19:1] noe/nrd nwr0/nwe nwr1/nub ncs[2:0] d[15:0] capt0 pwm1 pwm2 pwm3 pllrc capt1 add20/cs3 add0/nlb test tms tdo tdi tck scanen vddcore gnd irq[1:0] fiq spi usart0 tc0 ebi jtag select mcki mcko rtcki clk/upio rtcko pio pio st0 usart1 pio tc1 pio tc2 pio tc0 pio pwm ch0 ch1 ch2 ch3 pio coreclk 3v 3v 5v 5v analog 5v 3v 5v ch0 ch1 st1 ch0 ch1 5v capture 1 pdc channel pdc channel lfclk pio[31:0] gnd canrx3 cantx3 clock controller with pll 2 pdc channels 2 pdc channels 2 pdc channels advanced memory controller embedded ice arm7tdmi core i/o power supply core power supply generic interrupt controller reset 10 channel pdc controller arbiter asb controller sfm amba tm bridge internal sram 16 kb watch dog simple timers upio t1tioa0/mpio t1tiob0/mpio t1tclk0/mpio t0tioa2/mpio t0tiob2/mpio t0tclk2/mpio t0tioa1/mpio t0tiob1/mpio t0tclk1/mpio t0tioa0/mpio t0tiob0/mpio t0tclk0/mpio rxd1/mpio txd1/mpio sck1/mpio rxd0/mpio txd0/mpio sck0/mpio spck/mpio miso/mpio mosi/mpio npcs0/mpio npcs1/mpio npcs2/mpio npcs3/mpio timer t0 timer t1 analog power suppy 1 pdc channel 1 pdc channel adc0 8-channel 10-bit adc adc1 8-channel 10-bit adc can0 full speed 16 buffers can1 full speed 16 buffers can3 full speed 16 buffers can2 full speed 32 buffers watch timer capture 0 nwait/upio
3 preliminary AT91SAM7A2 - summary 6021bs?atarm?07/04 pin configuration table 1. pinout pin name pin name pin name pin name 1 vddio 45 gnd 89 vddio 133 noe/nrd 2 irq0 46 vddio 90 vddana 134 ncs0 3 irq1 47 upio5 91 vrefp0 135 add1 4 fiq 48 upio6 92 ana0in0 136 d9 5 sck0/mpio 49 gnd 93 ana0in1 137 d2 6 txd0/mpio 50 vddio 94 ana0in2 138 vddcore 7 rxd0/mpio 51 upio7 95 ana0in3 139 d10 8 sck1/mpio 52 upio 8 96 ana0in4 140 d3 9 txd1/mpio 53 upio 9 97 ana0in5 141 d11 10 rxd1/mpio 54 upio 10 98 ana0in6 142 d4 11 vddcore 55 upio 11 99 gnd 143 d12 12 cantx3 56 upio 12 100 vddana 144 d5 13 canrx3 57 upio 13 101 ana0in7 145 d13 14 capt0 58 upio 14 102 vrefp1 146 d6 15 capt1 59 upio 15 103 ana1in0 147 d14 16 spck/mpio 60 upio 16 104 ana1in1 148 d7 17 miso/mpio 61 upio 17 105 ana1in2 149 d15 18 mosi/mpio 62 upio 18 106 ana1in3 150 gnd 19 npcs0/mpio 63 gnd 107 ana1in4 151 add0/nlb 20 vddio 64 vddio 108 ana1in5 152 add17 21 gnd 65 upio19 109 ana1in6 153 add16 22 npcs1/mpio 66 upio20 110 ana1in7 154 add15 23 npcs2/mpio 67 upio21 111 gnd 55 add14 24 npcs3/mpio 68 upio22 112 vddcore 156 add13 25 t0tioa0/mpio 69 upio23 113 rtcki 157 add12 26 t0tiob0/mpio 70 upio24 114 rtcko 158 add11 27 t0tclk0/mpio 71 upio25 115 gnd 159 add10 28 t0tioa1/mpio 72 upio26 116 vddcore 160 add9 29 t0tiob1/mpio 73 upio27 117 scanen 161 add20/cs3 30 t0tclk1/mpio 74 upio28 118 test 162 vddcore 31 t0tioa2/mpio 75 upio29 119 tms 163 nwr0/nwe 32 t0tiob2/mpio 76 upio30/nwait 120 tdo 164 ncs2 33 vddio 77 upio31/coreclk 121 tdi 165 ncs1 34 gnd 78 cantx0 122 tck 166 add19 35 t0tclk2/mpio 79 canrx0 123 gnd 167 add18 36 t1tioa0/mpio 80 cantx1 124 pllrc 168 add8 37 t1tiob0/mpio 81 canrx1 125 vddcore 169 add7 38 t1tclk0/mpio 82 cantx2 126 mcki 170 add6 39 nreset 83 canrx2 127 mcko 171 add2 40 upio0 84 pwm0 128 gnd 172 add3 41 upio1 85 pwm1 129 nwr1/nub 173 add4 42 upio2 86 pwm2 130 d8 174 add5 43 upio3 87 pwm3 131 d1 175 gnd 44 upio4 88 gnd 132 d0 176 gnd
4 preliminary AT91SAM7A2 - summary 6021bs?atarm?07/04 figure 2. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 132 131 130 129 144 143 142 141 140 139 138 137 136 135 134 133 156 155 154 153 152 151 150 149 148 147 146 145 168 167 166 165 164 163 162 161 160 159 158 157 176 175 174 173 172 171 170 169
5 preliminary AT91SAM7A2 - summary 6021bs?atarm?07/04 signal description table 2. signal description module name function type active level comments ebi add[19:1] external address bus o (z) (1) the ebi is tri-stated when nreset is at a logical low level. internal pull-downs on data bus bits add0/nlb external address line line/ lower byte enable ol (z) add20/cs3 external address line/ chip select o h (z) d[15:0] external data bus i/o (z) noe output enable o l (z) nwr0/nwe write enable o l (z) ncs[2:0] chip select lines o l (z) nwr1/nub upper byte enable o l (z) nwait external wait i l disable at reset, multiplexed with upio30 coreclk core clock o disable at reset, multiplexed with upio31 gic irq[1:0] external interrupt lines i fiq fast interrupt line i power-on reset nreset hardware reset input i l schmitt input with internal filter master clock mcki master clock input i connected to external crystal (4 to 6 mhz) mcko master clock output o pllrc pll rc network input i 32.768 khz clock rtcki 32.768 khz clock input i connected to external 32.768 khz crystal rtcko 32.768 khz clock output o pio upio[31:0] general purpose i/o i/o (z) usart0 sck0/mpio usart0 clock line i/o (z) multiplexed with general purpose i/o rxd0/mpio usart0 receive line i/o (z) multiplexed with general purpose i/o txd0/mpio usart0 transmit line i/o (z) multiplexed with general purpose i/o usart1 sck1/mpio usart1 clock line i/o (z) multiplexed with general purpose i/o rxd1/mpio usart1 receive line i/o (z) multiplexed with general purpose i/o txd1/mpio usart1 transmit line i/o (z) multiplexed with general purpose i/o capture0 capt0 capture input i capture1 capt1 capture input i pwm pwm[3:0] pulse width modulation output o (l) timer t0 t0tioa[2:0]/mpio capture/waveform i/o i/o (z) multiplexed with a general purpose i/o t0tiob[2:0]/mpio trigger/waveform i/o i/o (z) multiplexed with a general purpose i/o t0tioclk[2:0]/mp io external clock/trigger/input i/o (z) multiplexed with a general purpose i/o
6 preliminary AT91SAM7A2 - summary 6021bs?atarm?07/04 note: 1. values in brackets are the values at reset (h = high, l = low, z = high impedance state). timer t1 t1tioa/mpio capture/waveform i/o i/o (z) multiplexed with a general purpose i/o t1tiob/mpio trigger/waveform i/o i/o (z) multiplexed with a general purpose i/o t0tioclk/mpio external clock/trigger/input i/o (z) multiplexed with a general purpose i/o adc0 ana0in[7:0] analog input i vrefp0 positive voltage reference i adc1 ana1in[7:0] analog input i vrefp1 positive voltage reference i spi spck/mpio spi clock line i/o (z) multiplexed with a general purpose i/o miso/mpio spi master in slave out i/o (z) multiplexed with a general purpose i/o mosi/mpio spi master out slave in i/o (z) multiplexed with a general purpose i/o npcs[3:1]/mpio spi chip select i/o (z) multiplexed with a general purpose i/o npcs0/nss/mpio spi chip select (slave input) i/o (z) multiplexed with a general purpose i/o can0 canrx0 can0 receive line i l cantx0 can0 transmit line o l (h) can1 canrx1 can1 receive line i l cantx1 can1 transmit line o l (h) can2 canrx2 can2 receive line i l cantx2 can2 transmit line o l (h) can3 canrx3 can3 receive line i l cantx3 can3 transmit line o l (h) jtag scanen scan enable i h internal pull-down (connected gnd or leave unconnected) tdi test data in i schmitt trigger, internal pull-up tdo test data out o tms test mode select i schmitt trigger, internal pull-up tck test clock i schmitt trigger, internal pull-up test factory test i h internal pull-down (connected gnd or leave unconnected) power supplies vddcore core power supply - 3.3v vddana analog power supply - 3.3v vddio i/o lines power supply - 3.3v to 5v gnd ground - table 2. signal description (continued) module name function type active level comments
7 preliminary AT91SAM7A2 - summary 6021bs?atarm?07/04 architectural overview the AT91SAM7A2 architecture consists of two main buses, the advanced system bus (asb) and the advanced peripheral bus (apb). the asb is designed for maximum performance. it interfaces the processor with the on-chip 32-bit memories and the external memories and devices by means of the external bus interface (ebi). the apb is designed for access to on- chip peripherals and is optimized for low power consumption. the amba ? bridge provides an interface between the asb and the apb. the AT91SAM7A2 peripherals are designed to be programmed with a minimum number of instructions. each peripheral has a 16 kbyte address space allocated in the upper 1 mbytes of the 4 gbyte address space. except for the interrupt controller, the peripheral base address is the lowest address of its memory space. the peripheral register set is composed of control, mode, data, status and interrupt registers. to maximize the efficiency of bit manipulation, fre- quently written registers are mapped into three memory locations. the first address is used to set the individual register bits, the second resets the bits and the third address reads the value stored in the register. a bit can be set or reset by writing a one to the corresponding position at the appropriate address. writing a zero has no effect. individual bits can thus be modified with- out having to use costly read-modify-write and complex bit manipulation instructions. the arm7tdmi processor operates in little-endian mode in the AT91SAM7A2 microcontrol- ler. the processor's internal architecture and the arm and thumb instruction sets are described in the arm7tdmi datasheet. amc: advanced memory controller the AT91SAM7A2 embeds 16 kbytes of internal sram. the internal memory is directly con- nected to the 32-bit data bus and is single-cycle accessible. this provides maximum performance of 27 mips @ 30 mhz by using the arm instruction set of the processor, mini- mizing system power consumption and improving on the performance of separate memory solutions. ebi: external bus interface the ebi generates the signals which control the accesses to the external memories or periph- eral devices. the ebi is fully programmable and can address up to 6 mbytes. it has four chip selects and a 21-bit address bus, the upper bit of which is multiplexed with a chip select. sep- arate read and write control signals allow for direct memory and peripheral interfacing. the ebi supports different access protocols allowing single clock cycle memory accesses. the main features are: external memory mapping up to four chip select lines byte write or byte select lines 8-bit or 16-bit data bus external wait remap of boot memory two different read protocols programmable wait state generation gic: generic interrupt controller the AT91SAM7A2 has an 8-level priority, individually maskable, vectored interrupt controller. this feature substantially reduces the software and real time overhead in handling internal and external interrupts. the interrupt controller is connected to the nfiq (fast interrupt request) and the nirq (standard interrupt request) inputs of the arm7tdmi? processor. the proces- sor's nfiq line can only be asserted by the external fast interrupt request input: fiq. the nirq line can be asserted by the interrupts generated by the on-chip peripherals and the external interrupt request lines: irq0 to irq1. an 8-level priority encoder allows the customer to define the priority between the different nirq interrupt sources. internal sources are programmed to
8 preliminary AT91SAM7A2 - summary 6021bs?atarm?07/04 be level sensitive or edge triggered. external sources can be programmed to be positive or negative edge triggered or high or low level sensitive. pio: parallel i/o controller the AT91SAM7A2 has 57 configurable i/o lines . 32 pins (united pio) on the AT91SAM7A2 are dedicated as general purpose i/o pins (upio0 to upio31). other i/o lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. the united-pio is controlled by a dedicated module. the others pins are configure in each module. pdc: peripheral data controller an on-chip, 10-channel peripheral data controller (pdc) transfers data between the on-chip peripherals and the on and off-chip memories without processor intervention. one pdc chan- nel is connected to the receiving channel and one to the transmitting channel of each usart and of the spi. a single pdc channel is connected to each adc and each capture. most importantly, the pdc removes the processor interrupt handling over-head and signifi- cantly reduces the number of clock cycles required for a data transfer. it can transfer up to 64 kbytes without reprogramming the starting address. as a result, the performance of the micro- controller is increased and the power consumption reduced. usart: universal synchronous asynchronous receiver transmitter the AT91SAM7A2 provides two identical, full -duplex, universal synchronous asynchronous receiver transmitter which are connected to the peripheral data controller. the main features are: programmable baud rate generator parity, framing and overrun error detection line break generation and detection automatic echo, local & remote loopback modes multi-drop mode: address detection and generation interrupt generation two dedicated peripheral data controller channels 5-, 6-, 7-, 8- and 9-bit character length idle flag for j1587 protocol. smart card transmission error feature support lin 1.2 protocol with h/w layer spi: serial peripheral interface the AT91SAM7A2 features an spi that provides communication with external devices in mas- ter or slave mode. the spi has four external chip selects that can be connected to up to 15 devices. the data length is programmable from 8- to 16-bit. as for the usart, a two-channel pdc is used to move data directly between memory and the spi without cpu intervention for maximum real-time processing throughput. can: controller area network the AT91SAM7A2 provides four cans (2.0a and 2.0b). these are based upon serial commu- nications protocol which efficiently supports distributed real-time control with a very high level of security (one with 32 mailboxes and the others with 16 mailboxes). the main features are: prioritization of messages multi-master system wide data consistency error detection and error signaling automatic retransmission of corrupted messages
9 preliminary AT91SAM7A2 - summary 6021bs?atarm?07/04 automatic reply after receive a remote frame time stamp on each transfer multicast reception with time synchronization continuous reception mode gpt: general purpose timer the AT91SAM7A2 features four general pu rpose timers. each timer can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. each general purpose timer has one external clock input, five internal clock inputs, and three multi-purpose input/output signals which can be configured by the user. each timer drives an internal interrupt signal which can be programmed to generate processor interrupts via the aic (advanced interrupt controller). three general purpose timers are grouped in the same block. this block has two global reg- isters which act upon all three gpts. the block control register allows the three timers to be started simultaneously with the same instruction. the block mode register defines the exter- nal clock inputs for each timer, allowing them to be chained. st: simple timer simple timers provide basic functions for timing calculation. each channel of this timer has a specific prescalar and a 16-bit counter. the prescalar defines the clock frequency of the chan- nel counter. the 16-bit counter starts down-counting when a value different than zero is loaded. an interrupt is generated when the counter is null. capt: capture module the capture module is a frame analyzer. it stores the period of time between two edges of a signal in a register. this period is described as a number of counter cycles. the capture allows data transfers with the pdc. pwm: pulse width modulation the AT91SAM7A2 includes four pwm channels. each channel can generate pulses. the fre- quency and the duty cycle of each channel can be configured. wt: watch timer the watch timer provides a seconds counter and an alarm function. the alarm register has a resolution of 30.5 s. this allows a 32-bit register to have sufficient range to cater for a 24 or 36 hour period. wd: watch dog the AT91SAM7A2 has an internal watchdog which can be used to prevent system lock-up if the software becomes trapped in a deadlock. sfm: special function module the AT91SAM7A2 provides registers which implement the following special functions. chip identification reset status
10 preliminary AT91SAM7A2 - summary 6021bs?atarm?07/04 adc: analog to digital converter the two identical 8-channel 10-bit analog-to-digital converters (adc) are based on a succes- sive approximation register (sar) approach. each adc has 8 analog input pins, ana0in0 to ana0in7 and ana1in0 to ana1in7, and provides an interrupt signal to the aic. both adcs share the analog power supply pins v dda and gnda, and the input reference voltage pin v refp . each channel can be enabled or disabled independently, and has its own data register. the adc can be configured to automatically enter sleep mode after a conversion sequence, and can be triggered by the software. the adc allows a data transfer with the pdc. pmc: power management controller the AT91SAM7A2 power management controller allows optimization of power consumption. the pmc enables/disables the clock inputs of the pdc and arm core. moreover, the main oscillator, the pll and the analog peripherals can be put in standby mode allowing minimum power consumption to be obtained. the pmc provides the following operating modes: normal: the clock generator provides clock to chip. wait mode: the arm core clock is deactivated. slow mode: the clock generator is deactivated, the system is clocked at 32.768 khz. each peripheral clock can be independently stopped or started directly in the peripheral to fur- ther reduce power consumption in normal, wait and slow modes. ice debug mode arm standard embedded in circuit emulation is supported via the ice port. it is connected to a host computer via an external ice interface. in ice debug mode the arm core responds with a non-jtag chip id which identifies the co re to the ice system. this is not jtag ieee 1149.1 compliant.
11 preliminary AT91SAM7A2 - summary 6021bs?atarm?07/04 ordering information table 3. ordering information ordering code package temperature operating range AT91SAM7A2-ai tqfp 176 industrial (-40c to +85c)
12 preliminary AT91SAM7A2 - summary 6021bs?atarm?07/04 packaging information package drawing figure 3. 176-lead lqfp package drawing p in 1 a aa b bb c c 1 d dd s l 1 r 1 r 2 0 .25 c cc 1
13 preliminary AT91SAM7A2 - summary 6021bs?atarm?07/04 table 4. package dimensions (mm) symbol min nom max c 0.09 0.20 c1 0.09 0.16 l 0.45 0.6 0.75 l1 1.00 ref r2 0.08 0.2 r1 0.08 s0.2 q0 3.5 7 10 211 12 13 311 12 13 a 1.6 a1 0.05 0.15 a2 1.35 1.4 1.45 tolerances of form and position aaa 0.2 bbb 0.2 table 5. lead count dimensions (mm) pin count d/e bsc d1/e1 bsc bb1 e bsc ccc ddd min nom max min nom max 176 26.0 24.0 0.17 0.20 0.27 0.17 0.20 0.23 0.50 0.10 0.08 table 6. device and 176-lead lqfp package maximum weight 1900 mg
14 preliminary AT91SAM7A2 - summary 6021bs?atarm?07/04 soldering profile table 7 gives the recommended soldering profile from j-std-20. small packages may be subject to higher temperat ures if they are reflowed in boards with larger components. in this case, small packages may have to withstand temperatures of up to 235c, not 220c (ir reflow). recommended package reflow conditions depend on package thickness and volume. see table 8 below. notes: 1. the packages are qualified by atmel by using ir reflow conditions, not convection or vpr. 2. by default, the package level 1 is qualified at 220c (unless 235c is stipulated). 3. the body temperature is the most important parameter but other profile parameters such as total exposure time to hot temperature or heating rate may also influence component reliability. a maximum of three reflow passes is allowed per component. table 7. soldering profile convection or ir/convection vpr average ramp-up rate (183 c to peak) 3 c/sec. max. 10 c/sec. preheat temperature 125 c 25 c 120 sec. max temperature maintained above 183 c 60 sec. to 150 sec. time within 5 c of actual peak temperature 10 sec. to 20 sec. 60 sec. peak temperature range 220 +5/-0 c or 235 +5/-0 c 215 to 219 c or 235 +5/-0 c ramp-down rate 6 c/sec. 10 c/sec. time 25 c to peak temperature 6 min. max table 8. recommended package reflow conditions (1, 2, 3) parameter temperature convection 220 +5/-0 c vpr 215 to 219 c ir/convection 220 +5/-0 c
printed on recycled paper. preliminary disclaimer: atmel corporation makes no warranty for the use of its produc ts, other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained her ein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel produc ts, expressly or by implication. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature 6021bs?atarm?07/04 ? atmel corporation 2004 . all rights reserved. atmel ? and combinations thereof, are the register ed trademarks of atmel corporation or its subsidiaries. arm ? , arm7tdmi ? , arm ? thumb ? and arm powered ? are the registered trademarks and amba ? is the trademark of arm ltd. other terms and product names may be the trademarks of others. 0m
16 preliminary AT91SAM7A2 - summary 6021bs?atarm?07/04

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